The integration, during semiconductor device fabrication, of non-volatile memory (NVM) devices with other device structures, such as high voltage transistors and low voltage logic devices, is challenging. This is at least in part due to the different performance and/or operating requirements of the NVM devices, which store charge, and the other devices, which perform other functions. Accordingly, for some known semiconductor device fabrication processes, the high and low voltage devices are defined together in separate processing steps from the forming of the NVM devices. However, even this approach is becoming increasingly challenging. For example, a much reduced thermal budget and much thinner gate polysilicon and gate spacers make it difficult to obtain satisfactory breakdown voltages for the high voltage devices without incurring additional process cost and complexity.
Embodiments of the present disclosure are illustrated by way of example and are not limited by the accompanying figures. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to help to improve understanding of the embodiments.
The apparatus and method components have been represented where appropriate by conventional symbols in the drawings. Some drawings show only those specific details that are pertinent to understanding the embodiments, so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein. Also, the functions included in any flow diagrams do not imply a required order of performing the functionality contained therein.